Circuit Design of SPI Electronic Paper Display - Selection of MOS Tubes
- Categories:Technical Support
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- Time of issue:2022-10-25 22:04
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(Summary description)
Circuit Design of SPI Electronic Paper Display - Selection of MOS Tubes
(Summary description)
- Categories:Technical Support
- Author:
- Origin:
- Time of issue:2022-10-25 22:04
- Views:
Circuit Design of SPI Electronic Paper Display - Selection of MOS Tubes
We suggest that the MOS tube should use Si1304BDL or Si1308EDL.
MOSFETsVBsemiSI1304BDL
Spec: 487ed739fd7bf4abe2bed04936ead327.pdf
Configuration: Single
Threshold voltage Vgs (th): 1.3V
FET type: N-Channel
Package: Tape/reel
Drain source conduction resistance RDS (on): 36m Ω
Power dissipation: 2.8W
Grid source breakdown voltage: ± 12V
Drain source breakdown voltage BVDSS: 20V
Polarity: N-Channel
Component lifecycle: Active
Storage temperature: - 55~+150 ℃
Number of pins: 3Pins
Height: 1.10mm
L x W/D: 2.00 x 1.25mm
Authentication information: RoHS, HF (halogen free)
Minimum package: 3000 pcs
Country of origin: America
Original manufacturer: VBsemi Electronics Co. Ltd
Brand: VBsemi
Grid charge: 8.8nC
Lead free or not: Yes
Part status: Active
Drain source voltage (Vdss): 20V
Continuous drain current Id@25 ℃ : 1A
Working temperature (Tj): - 55~+150 ℃
Installation type: SMT
Package/housing: SC70
N-channel drain source voltage (Vdss): 20V continuous drain current (Id): 4A power (Pd) 2.8W
SI1308EDL-T1-GE3
Spec :https://www.findic.com/doc/browser/keRaOEwdL?doc_id=59485237#locale=zh-CN
Number of pins 3
Drain source resistance 0.11 Ω
Polarity N-Channel
Dissipated power 0.4 W
Threshold voltage 600 mV
Input capacitance 105 pF
Drain source voltage (Vds) 30 V
Continuous drain current (Ids) 1.5A
Rise time 20 ns
Input capacitance (Ciss) 105pF @ 15V (Vds)
Rated power (Max) 500 mW
Drop time 12 ns
Operating temperature (Max) 150 ℃
Operating temperature (Min) - 55 ℃
Dissipated power (Max) 400 mW
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